https://harishch4.github.io/Notes on compiler engineering, LLVM, MLIR, computer architecture, heterogeneous runtimes, and efficient AI inference. 2026-08-17T16:33:23+05:30 Harish https://harishch4.github.io/ Jekyll © 2026 Harish /assets/img/favicons/favicon.ico /assets/img/favicons/favicon-96x96.png 2026-08-17T12:00:00+05:30 2026-08-17T16:33:01+05:30 https://harishch4.github.io/posts/evaluating-llvm-instruction-scheduling-for-rocket-rv32/ Harish

Following an RV32 dot product through LLVM's machine scheduler, then reading the real llvm-mca output for the instruction order before and after scheduling.

2026-08-17T12:00:00+05:30 2026-08-17T12:00:00+05:30 https://harishch4.github.io/posts/how-llvm-schedules-risc-v-machine-instructions/ Harish

Following a small RISC-V instruction sequence through LLVM's dependency graph, ready queues, and scheduling decisions.

2026-08-17T12:00:00+05:30 2026-08-17T12:00:00+05:30 https://harishch4.github.io/posts/how-llvm-models-risc-v-processor-latency-and-resources/ Harish

Building LLVM's RISC-V scheduling model from the hardware questions established by instruction pipelining, forwarding, and instruction-level parallelism.

2026-08-17T12:00:00+05:30 2026-08-17T12:19:50+05:30 https://harishch4.github.io/posts/pipeline-dependencies-forwarding-and-instruction-level-parallelism/ Harish

Following values through an in-order RISC-V pipeline to understand forwarding, stalls, scoreboards, and where instruction-level parallelism comes from.

2026-08-17T12:00:00+05:30 2026-08-17T12:19:31+05:30 https://harishch4.github.io/posts/instruction-pipelining-in-an-in-order-risc-v-processor/ Harish

Starting from the hardware problem that makes instruction pipelining necessary, then following a concrete RISC-V instruction sequence to the first limit on overlap.